PCBgogo

Keep breakout vias open on the bottom and do a JTAG boundary scan? But you've got to be wary of shorts at the bottom by runaway solder paste from decoupling caps under BGA.
It all really depends on ball pitch. At 0.8 mm and up precise alignment is not important as the package with realign itself (to the point of course). I'm yet to encounter BGA soldering failure, but I'm only a hobbyist so it's not that much of a reassurance, but still considering how primitive the tools I'm using are (cheap-ass IR reflow oven, manual placement, only recently did I buy a manual stencil printer) I'm sure you'll be fine.
Anyway - what I do with my boards is create a test design that "wiggles" slowly such that neighboring balls wiggle at different frequency (to detect shorts), and then I go pin-by-pin and check if what I have on it matches what I expect. For balls that go to DDR3L I just create a test design with memory controller and MCU (really easy to do in Vivado) and run a memory stress test for several hours.
As I suggested many times here buy a bunch of cheap QSPI flash chips in BGA-24 package (can be had at lower than $1/piece) and refine your process with them. Larger parts are really "more of same", unless we're talking about really large (1000+ pins) packages.