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When we began this series, we observed that board-level designers often have concerns about the proper way to handle grounding for integrated circuits that have separate analog and digital grounds.

Part 1 focused on the basics: where the current flows. We learned that high-frequency signals flow not in the path of least resistance, but in the path of least impedance. We also discussed some fundamental principles of current flow in PCBs with ground planes.

In Part 2 we are now ready to apply these principles to the PCB layout of real-world circuits. We will learn how to place components and route signal traces to minimize problems with crosstalk. In Part 3 we consider power-supply currents and end that section by discussing how to extend what we have learned to circuits with multiple mixed-signal ICs.

Bypass Capacitors Are Important
As mentioned in Part 1, a more complete description of the current flow in any circuit includes the bypass capacitor at each IC and the power source. We start with the simplified two-IC circuit example from Part 1 (Figure 1).

We then include the bypass capacitors in Figure 2. This diagram shows the current paths with IC1 sourcing.

In this example there is a solid ground plane on a layer adjacent to the signal layer, which is assumed to be the component layer. Power is distributed on this top layer with the large metal traces shown in gray. Connections to the ground plane are made with vias from the green metal section on the signal layer to the ground plane.

The signal currents on the signal/component layer are shown with dashed lines. They are the easiest to understand, as they are strictly confined to the signal traces that we choose to place. The return currents have an entire plane over which they can flow.

Since DC currents will flow through the path of least resistance, we know that the DC return path will go directly from the ground pin of the load device, in this case IC2, to the ground connection of the power source by the shortest distance, a straight line. The high-frequency (transient) currents will flow under the signal trace with a distribution determined by the geometry of the trace and board.

We can dig deeper into the current flow for signals that are in-between cases. Start with frequencies low enough that a significant portion of the current flows from the power source, rather than virtually all of the current flowing from the capacitors. In this case there is still mutual inductance that will force the current to return under the signal trace, but the distribution will, of course, be much wider.

Also, once the return current under the trace reaches the IC, it will not all return to the capacitor ground. Instead, a percentage of the current sourced from the capacitor will return to its ground, while the rest will return to the power source ground. Finally, as the frequency gets lower the mutual inductance will have less and less effect; more current will flow through the DC path.

Fortunately, this in-between case is already managed by our efforts to handle the high-frequency and DC cases, as long as we also do a good job of both bypassing the ICs and distributing power properly. These later two items are really two facets of the same effort.

As the power source is moved farther away from the IC that it powers, the impedance - both resistance and inductance - between the two will increase. This also happens as the trace connecting the two decreases in width. The more impedance between the power source and the IC (remember to include the return impedance) that is exhibited by the interconnect, the more the bypass capacitor will be relied on for supplying lower frequency currents. Thus more capacitance is needed as the power source impedance increases.

So once again we must satisfy the requirement of adequate bypassing of power at the ICs.

For completeness, Figure3 shows the current flow when IC2 is sourcing.

Notice the interconnecting trace on the signal/component layer. We only changed the direction of the arrows for the signal current and the AC return current. In this case it is C2, the bypass capacitor for IC2, which supplies the AC signal current through IC2’s VDD pin to the signal pin on IC2. The signal current delivered to IC1 goes to ground through IC1’s ground pin; the AC portion returns on the ground plane under the signal path and the DC portion returns in a straight line to the power source.

Ground Is Not an Equipotential
At this point it is important to understand that a ground plane, despite what we were taught in EE 101, is not an equipotential. First of all, no matter how thick the copper is for your ground plane, it does have resistance. Therefore, if the analog and digital return currents (or any two currents) share a portion of the ground plane (i.e., their currents flow through the same metal) there will be crosstalk between the two as the copper resistance causes IR voltage drops.

Think of it this way: the ground pins of two different components connect to the ground plane at nearly the same point and their currents return to a single point at the other end of the board. Assume that the copper resistance of the plane along this path is 0.01Ω and that component A is sourcing 1A while the current from component B is 1mA. At the end where these components connect, the ground voltage will be 10mV greater than the ground voltage at the point where the currents return. Even component B, which is only putting out 1mA, will experience a 10mV rise over the return point. If the current from component A alternates from 1A to 0A, any voltage referenced to component B will vary up and down by 10mV along with this current.

Shared return paths often cause problems when digital circuits co-reside with analog circuits. The sharing can interfere with proper operation of a precision analog circuit.

Another cause of nonuniform voltages across a ground plane is electrical length. At higher frequencies the length of the current paths through the plane can be a significant percentage of the wavelength of the signals propagating on the board. We will not pursue this fact in this short article. It is enough to say that shorter is better.

Putting It All Together
With the basics of current flow on a PCB understood, we can start using this knowledge to properly handle the grounding of mixed analog-digital ICs. Ultimately, the goal is to ensure that the digital and analog currents do not share portions of the same return path.

By now you realize that the whole objective is to minimize commonality of return paths for the digital and analog signals. This is, in fact, the goal. If we do this, we will eliminate the major cause of problems when the "nasty" digital signals corrupt the "pristine" analog signals.

A common assumption is that one should cut the ground plane into a digital section and an analog section. This is a good starting point. As you will see, if we lay out everything properly, we can just fill in the cuts with no change in performance.

Cut the Ground Plane…for Now
We start with a generic ADC on a board as the only component with both analog and digital circuitry. Then we will determine where to cut the ground plane for a single point ground.

Figure 4 shows the pin connections for our ADC chip. Only the power and ground pins are labeled explicitly. The other labeling just indicates whether the connection is for an analog or digital pin; their specific functions are unimportant. An analog pin may be one of several signal input pins or a reference input or output. A digital pin may be part of a serial or parallel interface, a control pin, or a chip select. For our discussion, we treat them the same regardless of their specific function.

Note that the digital pins are contiguous, as are the analog pins with analog and digital ground adjacent. This is not uncommon, because chip designers must manage the same realities as board designers. Note also that there are two digital ground pins. This is sometimes necessary so that the ground currents in the chip do not cause problems as they run from one end of the chip to the other.

Since the analog and digital pins are grouped nicely here, it is very easy to decide where to put the (temporary) ground plane cuts.

We see the ground plane in blue in Figure 5 with the single-point ground right at the adjacent analog and digital ground pins. Generally when a cut ground plane is to be used like this, the designer puts all the digital chips and related components on one side of the cut and all the analog chips and related components on the other side. In this way their ground pins can connect to the correct portion of the ground plane. Recall that for this example our ADC is the only device with both analog and digital pins and signals.

Assume now that we did a fine job on this, that all the digital components are completely over the digital portion of the ground plane, and that all the analog components are over the other portion. We are not done yet. We have to consider the routing of signal traces.

Routing the Signal Traces
We begin with a digital signal from one of the other ICs in this design routed as shown in Figure 6.

This trace is routed over much of the analog section and crosses the ground cut in two places. Most designers would recognize this as bad form because it results in a digital trace in the analog area which can, therefore, contaminate analog signals. While that is true, the extent of the problem is often not fully appreciated. Consider where the AC current would return.

Figure 7 shows the return current in orange. Notice how it follows the signal trace until it encounters a cut. At that point it can only return through the single-point ground to get to the other side of the cut. Consequently, we not only have the digital current with its high-frequency content running through the analog circuitry’s ground - something we were trying to avoid - but we also have created two nice loop antennas that will radiate these signals.

For our ground cut method to work, we must ensure that the digital and analog components stay on their respective side of the cut and that the traces do too.

What happens when we meet this requirement? Figure 8 shows all the signal traces routed without crossing any ground cut. The return currents flow under the signal traces, minimizing the loop area because the only thing separating the signal traces from the ground plane is the thickness of the PCB itself.

Take a close look at the ground current in Figure 8. None of the currents "wants" to cross the ground plane cuts. This is because we have been careful to place components so that all the connections, digital or analog, are over their respective ground areas. Then we routed all traces to stay in the appropriate area. Since no currents are crossing the cuts, the cuts are serving no purpose and thus can be eliminated (i.e., filled in with metal).

Summary and Looking Forward
Where do we find ourselves now in this discussion of proper grounding of mixed signals for complex circuits? We have just applied the basic grounding principles presented in Part 1 of this series. We arranged components and traces on a mixed-signal PCB in a design which successfully minimizes signal-path crosstalk and yet does not need ground plane cuts.

In Part 3 of the series, Power Currents and Multiple Mixed-Signal ICs, we will consider how to manage the power-source currents and extend these techniques to designs with multiple mixed-signal chips. We finish with a case where a ground plane cut is useful.

References
Ott, Henry W., Electromagnetic Compatibility Engineering, John Wiley and Sons, Hoboken, NJ, 2009. ISBN 978-0-470-18930-6

Johnson, Howard W., Ph.D. and Graham, Martin, Ph.D., High-Speed Digital Design: A Handbook of Black Magic, Prentice-Hall, Upper Saddle River, NJ, 1993. ISBN 0-13-395724-1

Stoehr, Martin, "Avoid PC-Layout "Gotchas" in ISM-RF Products," Maxim Integrated Products application note 4636.