- Feb 26.2014, 14:57:00
In the field of network communications , ATM switches, core routers , Gigabit Ethernet, and a variety of gateway devices , the system data rate, clock rates increase , the corresponding processor ’s operating frequency is higher and higher ; transmission of data , voice, image rate has been far higher than 500Mbps, hundreds of megabytes or even several guitar backplane is also increasingly common. Down time means to improve system speed digital signals as short as possible , a series of high-speed design issues raise by the digital signal generated frequencies and edge rates are becoming increasingly prominent. When the signal interconnect delay is more than 20% of the time flipping edge signal , the signal wire board will be showing a transmission line effects , this design has become the high-speed design . Speed problem appears to hardware design brings greater challenges , from a logical point of view there are many correct design , if handled improperly in the actual PCB design will lead to failure of the entire design , the pursuit of this case in an increasingly high-speed network communication field more obvious. Experts predict that in the future the cost of the hardware circuit design , the logic design overhead will be greatly reduced and the overhead associated with the high-speed design will be 80 % of the total cost even more. High speed has become one of the important factors to the success of the system design .
Problems due to the high-speed signal overshoot , undershoot , reflections , ringing, crosstalk , etc. will seriously affect the normal timing system , reduce system timing margin of forcing people concerned about the impact the timing and quality of the digital waveform phenomena . Due to increased speed makes the timing becomes critical , regardless of the system in advance just how thorough understanding of the principles , can give any neglect and simplify the system have serious consequences . In the high-speed design , the impact is more critical timing issues , this article will be devoted to the design of high-speed timing analysis and simulation strategy.
1 common clock synchronization timing analysis and simulation
In high-speed digital circuits, transmission of data by the clock on the data are generally orderly and receive control signals . Chip can only send and receive data by timing requirements , long signal delay or signal delay matching may lead to improper signal timing violation and functional disorders. In low-speed system interconnect delay and ringing phenomenon can be negligible , because in such a low-speed signal system has enough time to reach steady state. However, in high-speed systems , the edge rate of speed , the system clock rate is increased , the signal transmission between the device and the synchronization time is shortened preparation time , the equivalent capacitance of the transmission line , the inductor will be converted to a digital signal is delayed and distorted , coupled with the signal delay mismatch and other factors will affect the chip to build and hold time , leading to the chip can not correctly receive the data , the system can not work properly.
The so-called common clock synchronization , refers to the transmission of data , the drive and the receiver on the bus share the same clock source , issue the same role in the same phase of the clock buffer clock (CLOCK BUFFER) , the completion of sending data and reception. Figure 1 shows a typical common clock synchronization data transceiver working schematic diagram . Figure 1, the crystal CRYSTAL produce an output signal reaches CLK_IN clock divider CLOCK BUFFER, issued with two -phase clock distribution buffers after CLOCK BUFFER , all the way to the CLKB, DRIVER for data output ; Another way is CLKA, for sampling latch DRIVER RECEIVER sent by the data . Tflt_CLKB CLKB clock period after the flight time (FLIGHT TIME) after arrival DRIVER, DRIVER internal data latched by the CLKB after TCO_DATA DRIVER time appears on the output port , then the output data after a flight time of arrival RECEIVER Tflt_DATA input port ; RECEIVER input port in use to generate another clock cLOCK BUFFER CLKA ( CLKA clock is delayed after the time of flight, i.e. Tflt_CLKA) DRIVER sampling latch data from the batch , thereby completing a data transfer clock cycles COMMON CLOCK process.
The above procedure showed the rising edge reaches RECEIVER data using a sampling clock of a cycle , whereby the transfer of data obtained by the two necessary conditions to be satisfied : ① the input set-up time data RECEIVER generally required Tsetup, it represents valid data must be valid at the minimum time clock , a data signal to the input of time should be sufficiently in advance of the clock signal , whereby the settling time can be drawn from the inequality satisfied ; ② to successfully latched data to the internal device , must be long enough to keep the data signal at the input of the receiver chip is valid to be sure the correct signal sampling latch clock , this time is called the hold time , the delay must be less than CLKA time invalid data (INVALID), whereby hold time can be drawn satisfied inequality .
1.1 Data Setup Time Series Analysis
From the first condition , the data signal must reach before the clock CLKA the receiving end , in order to properly latch the data. In the common bus clock , the function of the first clock cycle is latched into the data output terminal DRIVER , the second clock cycle the data is latched into the internal RECEIVER , which means that the data signal reaches the input time should RECEIVER early enough in the clock signal CLKA . To satisfy this condition , you must determine the clock and data signals arrive RECEIVER delay and guaranteed to meet the requirements of the receiving end of the set-up time , for any amount of time than the time required to build the extra time is to establish timing margin Tmargin. In the timing diagram in Figure 1 , all of the arrows line represents the data signal and the clock signal delay in the chip generated internally or transmission line , below the line indicates the arrow from the first valid clock edge to input data arrives RECEIVER total delay in the above line arrow indicates the receive clock CLKA the total delay . Effective from the first clock edge to input data arrives RECEIVER total delay is:
TCLKA_DELAY = TCO_CLKA + Tflt_CLKA
The total delay CLKA receive the next clock cycle as follows:
TCLKA_DELAY = TCYCLE + TCO_CLKA + Tflt_CLKA
To meet the data setup time must have :
Expand and consider such factors as the clock jitter Tjitter obtained after finishing :
(1 ) in TCYCLE a clock cycle of the clock ; during the first phase in parentheses is the maximum clock chip CLOCK BUFFER output clock CLKA, CLKB between the manual says that the output-output skew; second brackets cLOCK BUFFER chip output is two clock CLKA, CLKB , respectively, to reach the maximum delay and DRIVER RECEIVER difference . Formula ( 1) TCO_DATA means under certain test load and test conditions, from the clock trigger the start of the data appears at the output port, and reaches a test voltage Vmeas ( or VREF) threshold time interval , TCO_DATA size and chip logic delay when the buffer oUTPUT BUFFER characteristics , the output load conditions have a direct relationship , TCO is available on the chip data sheet .
( 1 ) From the formula , the adjustable part is actually only two : Tflt_CLKB_MIN-Tflt_CLKB_MAX and Tflt_DATA_SETTLE_DELAY_MAX. From time to meet the terms of the establishment of a single , Tflt_CLKA_MIN should be as large as possible , while Tflt_CLKB_MAX and Tflt_DATA_SETTLE_DELAY_MAX will have as small as possible . In essence, that requires the receiving clock comes late, the data come a little earlier .
1.2 Analysis of sequence data hold time
In order to successfully latched into the internal device data , the data must be kept long enough signal at the input of the receiver chip to ensure effective signal being correct sampling latch clock , this time called the hold time. In the common bus clock , the receiver buffer by the second data latch clock edge , while the drive end of the next data is latched to the data transmission side . Therefore, to meet the receiver end holding time must ensure valid data before the next data to the reception signal reaches the flip-flop latches , which requires the reception clock CLKA to delay less than the delay of the received data signal . Figure 1 is a timing diagram , the clock CLKA of the delay can be obtained :
TCLKA_DELAY = TCO_CLKA + Tflt_CLKA
The data delay:
TDATA_DELAY = TCO_CLKB + Tflt_CLKB + TCO_DATA + Tflt_DATA_SWITCH_DELAY
To meet the data retention time , you must have:
Expand , organize and consider factors such as clock jitter Tjitter , we have the following relationship :
Formula ( 2 ) , the first bracket is still within the maximum CLOCK BUFFER chip clock phase between the clock output ; continue in the second bracket can be understood as two output clock chip clock CLKA , CLKB , respectively , and reach DRIVER RECEIVER the maximum delay difference ; to meet data retention time , the actual adjustable section also only two , namely Tflt_CLKB_MIN-Tflt_CLKA_MAX and Tflt_DATA_SWITCH_DELAY_MIN. Just from the point of view to meet the hold time , Tflt_CLKB_MIN and Tflt_DATA_SWITCH_DELAY_MIN should be as large as possible , while Tflt_CLKA_MAX will have the smallest possible . That is putting up to meet the hold time , it is necessary to enable the receiver clock early , and the data will have to be late void (invalid).
In order to correctly receive the data , the data must be integrated into the setup time and hold time , that satisfy both ( 1) and ( 2). Analysis of these two inequalities can be seen only three ways to adjust : the transmit clock delay, clock delay and delay receiving data . Adjustment programs may be carried out : First, assume that the delay is exactly equal to the transmit clock receiver clock delay , namely (Tflt_CLKA_MIN-Tflt_CLKB_MAX) = 0 and (Tflt_CLKB_MIN-Tflt_CLKA_MAX) = 0 ( timing will later assume that these two equations generated deviation to be considered ) , then the data can be obtained through the simulation delay range , delay no solution if the data is returned above two equations , adjust clock delay sending or receiving clock delay . Here is the broadband network switches GLINK common clock synchronization data bus transceiver examples : First, assume that the delay is exactly equal to the transmit clock receiver clock delay , delay and then determine the scope of data into the parameters , ( 1 ) ( 2) and , respectively, becomes:
In inequality tips , combined with the actual PCB layout , determine Tflt_DATA_SETTLE_DELAY_MAX <1.1; Tflt_DATA_SWITCH_DELAY_MIN> -0.1, the remaining margin of 0.4ns assigned to the time difference between two clocks and Tmargin. Extraction SPECCTRAQUEST topological and signal integrity simulation, and to determine the length of each segment and topology. This structure ( 12 combinations ) full scan simulation, : Tflt_DATA_SETTLE_DELAY_MAX = 1.0825, Tflt_DATA_SWITCH_DELAY_MIN = -0.0835004, meets to determine the range of 1.1 and -0.1 indicators . It can be concluded constraint rules GLINK bus data lines : ① matching resistor to delay the sending end should not be greater than 0.1ns; ② 0.1ns data line must match that each data line must be at 0.65ns ~ 0.75ns between . With the above constraint rules can guide the wiring .
Consider the following mandatory : Tflt_CLKA_MIN-Tflt_CLKB_MAX = 0 and influence Tflt_CLKB_MIN-Tflt_CLKA_MAX = 0 brings . Prior restraints transmit clock and receive clock exactly the same length ( in practice to match 0.02ns ) in CADENCE environment , the clock simulation results obtained : | Tflt_CLKA_MIN-Tflt_CLKB_MAX | <0.2 and | Tflt_CLKB_MIN-Tflt_CLKA_MAX | <0.2. Tmargin seen leaving a margin of 0.2ns.
The final simulation results are: ① matched resistors to delay the sending end should not be greater than 0.1ns; ② 0.1ns data lines to match , that is, each data line must be between 0.65ns ~ 0.75ns; ③ transmit and receive clocks clock to 0.02ns matching long ; ④ Tmargin = 0.2ns. With the above topology model and constraint rules can be SPECCTRAQUEST or imported into CONSTRAINS MANAGER in ALLEGRO . When these design constraints rules set up, you can use the rules autorouter drive automatic routing or manual transfer line .
2 source synchronous timing relationships and simulation
Refers to the so-called source-synchronous clock strobe signal CLK is accompanied by a driver chip to send data sent along , it is not as common clock synchronization that uses a separate clock source. In a source synchronous data transmission and reception , the data is first sent to the receiver, the clock is gated by a shorter time and then send these data to the receiving end for sampling latch . Its schematic diagram shown in Figure 2 . Timing analysis of the source synchronous clock synchronization is more common than the simple analysis method is very similar to the analysis given directly below formula:
Settling time : Tvb_min + (Tflt_clk_min-Tflt_data_settle_delay_max)-Tsetup-Tmargin> 0
Hold Time : Tva_min + (Tflt_data_switch_delay min-Tflt_clk _max)-Thold-Tmargin> 0
Which , Tvb settling time for the drive end , which means that the driver -side data much time on the clock valid and effective before ; Tva for the sending end of hold time , which means that the driver -side data remains valid after the effective time clock ; other parameters the same meaning as before . Below are common communication circuit introduces source-synchronous interface as an example TBI timing analysis and simulation processes. TBI interfaces including the transmit clock and transmit data 10bit and 10bit both receive clock and receive data . RBC0, RBC1 two receive clocks in the Gigabit Ethernet , the two clock frequencies 62.5MHz, a difference of 180 °, the two rising edges of the clock used to latch data in turn . According to the data sheet timing parameters into the above equation can be obtained:
To copy the analysis method : Assuming a clock , a data signal line , the flight time strictly equal , i.e. perfectly matched clock and data and then analyze the impact they do not match . The above equation becomes:
Visible , whether it is to establish the time or hold time has a significant margin. After simulation , the discovery data and clock exactly matching length ( 0.02ns to match , for example) , there are still differences between 0.3ns , i.e.,
Take Tmargin = 0.5ns get clock and data matching is 0.2ns, that matches the length of the data and clock should not exceed 0.2ns.
In an actual simulation analysis and simulation carried out on the first clock signal and the data integrity of the received waveform is preferably obtained by a suitable termination match. Figure 3 is a set of passive and active client -side match to match different clock line simulation waveform comparison , which you can see the necessity of signal integrity simulation performed first.
In common clock synchronization , sending and receiving data must be completed in one clock cycle . At the same time delay and delay device PCB traces also limits the maximum operating frequency of the theory of public clock bus. Therefore, the general public clock synchronization for less than the transfer rate of 200MHz ~ 300MHz , higher than the rate of transmission , the general source synchronous technology should be introduced . Work in synchronization source relative to the clock system , the parallel transmission of data and clock using the transmission rate is determined mainly by the difference between the data and the clock signal , so that the system can achieve higher transfer rates. By the author of broadband Ethernet switch and host daughter card board signal integrity analysis , timing analysis and simulation , greatly shorten the product design cycle , through analysis and simulation effectively address emerging high-speed signal integrity design , timing , etc. questions , and fully guarantee the quality and design speed design truly once-through PCB board. Motherboard and daughter card board now through debugging , and successfully converting.