日本語
****
How do you denote a plugged and plated via?
229
1
Jun 17.2019, 09:50:10
Some of the vias on our PCB are thermal vias, and they are to be plated over with copper, and plugged with epoxy.
However, other vias on the same PCB are normal vias, and are not to be plated over, and not to be plugged.
How do we denote this to the PCB assembler? The information doesn’t appear on the gerbers.
However, other vias on the same PCB are normal vias, and are not to be plated over, and not to be plugged.
How do we denote this to the PCB assembler? The information doesn’t appear on the gerbers.
- Comments(1)
Upload a photo:You can only upload 1 files in total. Each file cannot exceed 2MB.Supports JPG, JPEG, GIF, PNG, BMP
A****min
Jun 18.2019, 09:12:03
Epoxy plugged vias wouldn't seem to do much for thermals; don't you want them to fill with solder? Is the plug resin a thermally conductive epoxy?
As mentioned, there is no official formatted method to denote this; it goes on the fab drawing. PCB fabs -- the good ones anyway -- do in fact read all the notes and try to comply with as many of them as possible.
