CoPoS (Chip-on-Panel-on-Substrate): Will it Replace CoWoS for Next-Gen AI GPU Packages?

KEY TAKEAWAYS
 CoPoS is unlikely to replace CoWoS across the market in the next few years. It offers a more area-efficient panel format for very large AI GPU packages, but panel warpage, fine-line RDL yield, alignment, inspection, and capacity must mature first. The practical outcome is coexistence, with CoPoS entering the designs that benefit most.

The next AI package is not limited only by transistor density. It is also limited by how many compute dies and HBM stacks can be connected inside one manufacturable package.

That is why CoPoS has moved from a packaging acronym to a product planning question. This article separates proven capability from roadmap claims and shows what the change means for the PCB beneath the package.

What CoPoS Is and What It Is Not

CoPoS is a chip-on-panel-on-substrate packaging concept that builds the high-density interconnect structure in a panel format before attaching it to a package substrate. CoWoS performs the comparable chip integration step on a circular wafer. The CoPoS change is mainly a manufacturing format change, although it can enable different package sizes and economics.

A public 2026 industry roadmap identifies a 310 x 310 mm panel. That square contains 96,100 mm2 of gross area. A 300 mm wafer has about 70,686 mm2, so the panel has roughly 36 percent more geometric area before edge exclusions, keepouts, test structures, and yield loss are counted.

The CoPoS area comparison is useful but incomplete. A larger carrier does not guarantee more good packages because one RDL defect, placement error, or local warpage excursion can destroy value in a costly multi-die assembly. The correct business metric is cost per qualified package, not packages drawn on an ideal panel map.

CoPoS is also not a PCB-level chip attachment process. The finished AI module still connects through an organic package substrate and a BGA to the system PCB. It also does not automatically require a glass core; current reporting separates near-term panel development from commercial glass core adoption expected later.

Why AI Package Scaling Is Creating Demand for CoPoS

CoPoS addresses the growing mismatch between large rectangular AI layouts and round wafer processing. AI accelerators add compute chiplets, HBM stacks, local interconnect, and power delivery structures faster than a conventional package outline can expand economically.

At its 2026 North America Technology Symposium, TSMC stated that 5.5 reticle CoWoS was already in production. It also outlined a 14-reticle version for 2028 with approximately 10 large compute dies and 20 HBM stacks. This proves that CoWoS still has a substantial scaling roadmap, so panel processing is not the only route to larger AI systems.

The reason to consider CoPoS is therefore more specific. A square panel can reduce unusable perimeter area for large rectangular layouts, potentially raise output per carrier, and create room for packages that become awkward to place on a round wafer. Those CoPoS advantages matter most at sustained volume, where equipment and process qualification costs can be spread across many units.

TrendForce reported in June 2026 that 2026 was a supplier validation year for the 310 x 310 mm format, with pilot production targeted for 2027 and mass production forecast for the second half of 2028. Treat those dates as a roadmap, not a guaranteed source of qualified production capacity.

CoPoS and CoWoS Compared for Next Generation AI Packages

CoPoS and CoWoS should be compared by maturity, yield, package scaling, and total cost rather than by panel shape alone. The following CoPoS comparison table summarizes the decision from a hardware program perspective.

The table supports a cautious answer to the title question. CoPoS can replace CoWoS in selected product families if the panel flow delivers lower cost at the same reliability. It will not replace a mature platform simply because a square has more gross area.

What Must Be Solved Before CoPoS Can Scale

CoPoS must control several coupled process variables across a larger format before its theoretical area advantage becomes a repeatable manufacturing advantage.

• Warpage through the complete flow: The 2024 IEEE ECTC paper How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging identified CTE mismatch, epoxy molding compound shrinkage, carrier stiffness, die thickness, silicon content, and panel dimensions as interacting drivers. Warpage must remain controllable at every thermal and RDL step, not only at final inspection.

• Fine line RDL uniformity: Line width, spacing, via formation, plating thickness, and dielectric quality must stay consistent from the panel center to the corners. Local capability data is not enough; engineers need full panel maps and lot distributions.

• Placement and overlay accuracy: Large panels amplify the effects of thermal expansion and tool matching. Die placement, exposure, metrology, and inspection systems must share an alignment strategy that works after each heat cycle.

• Known good die economics: An AI package combines expensive logic and memory. Test coverage, repair strategy, and assembly sequence must prevent one weak element from turning the complete package into scrap.

• Equipment and material readiness: Panel size affects carriers, molding, lithography, plating, inspection, singulation, and factory handling. A pilot result becomes useful to customers only after materials, tools, recipes, and output capacity are qualified together.

These constraints explain why CoPoS is more likely to enter through a controlled product ramp than through a sudden industrywide switch.

What CoPoS Changes for the System PCB

CoPoS does not change the fundamental rules of PCB design, but the packages it enables can intensify escape routing, power, loss, heat, and flatness requirements. Board teams should wait for actual package interface data before locking the stackup.

• BGA escape and layer count: Start with the released ball map, breakout rules, and reference requirements. Route the highest density region first, then confirm laser microvia geometry, via-in-pad structure, dielectric thickness, and sequential lamination count with the PCB fabricator.

• Power distribution: Create a rail-by-rail current map from connectors and regulators to the BGA. Calculate DC voltage drop through planes, neck-downs, vias, and connector pins, then compare it with the package voltage tolerance and transient target impedance.

• High-speed channel loss: Use Dk and Df data at the frequencies used by the channel model. Include copper profile, glass style, via transitions, back drill residual stubs, connectors, and cables so the simulation represents the manufactured path.

• Board and package flatness: Review copper balance, board thickness, layer symmetry, stiffeners, heatsink or cold plate loading, and reflow support as one mechanical system. Large BGA coplanarity and PCB warpage can interact even when each part meets its standalone drawing.

• Assembly and test access: Plan paste aperture development, X-ray inspection, boundary scan, accessible test points, temperature sensing, and rework clearance before component placement is frozen. A thermally massive module can require a different assembly window from the surrounding board.

For fabrication review, send PCBgogo the proposed stackup, impedance table, back drill limits, finished copper by layer, package drawing, and validation requirements. These inputs align with its verified high layer count, HDI, controlled impedance, TDR, X-ray, and microsection capabilities and allow an engineering review based on the complete build.

A Practical CoPoS Era PCB Release Workflow

A CoPoS era PCB should move through five evidence-based gates before production files are released.

• 1 Package interface gate: Confirm the land pattern, ball map, keepouts, component height, allowable board deflection, mechanical loads, and package warpage across the assembly temperature range.

• 2 Stackup gate: Approve materials, substitution rules, finished copper, dielectric thickness, glass styles, copper profile, impedance targets, coupons, microvia structure, and back drill definition.

• 3 Electrical gate: Review channel loss and crosstalk, power plane resistance, target impedance, decoupling, connector current, return path continuity, and correlation measurements for the first article.

• 4 Mechanical and thermal gate: Approve board flatness, copper balance, stiffener and cold plate drawings, mounting sequence, fastener torque, airflow, thermal interface materials, and sensor locations.

• 5 Manufacturing validation gate: Define DFM review, impedance reports, electrical test, microsections, X-ray inspection, reflow profile, functional test, and reliability criteria before the purchase order.

This workflow is useful even before CoPoS reaches volume production because it prevents the advanced package from being treated as an ordinary BGA late in the board schedule.

Frequently Asked Questions About CoPoS

Will CoPoS Replace CoWoS for AI GPU Packages

Not across the market in the near term. CoWoS remains the production baseline, while CoPoS is still moving through validation and pilot capacity. Replacement is credible only where measured yield and cost per good package outperform the established flow.

Is CoPoS the Same as Fan Out Panel Level Packaging

No. They overlap in panel processing concepts, but fan-out panel-level packaging is a broad manufacturing category. CoPoS identifies a chip-on-panel-on-substrate architecture aimed at large, high-density packages.

Does CoPoS Always Use a Glass Panel or Glass Core

No. A panel can use different carrier and interconnect constructions, and the final package substrate is a separate element. Current 2026 reporting places widespread glass core commercialization later than the initial 310 x 310 mm panel roadmap.

How Does CoPoS Affect PCB Material Selection

It does not prescribe one PCB laminate. The correct material depends on channel loss, Dk and Df stability, copper roughness, thermal expansion, layer count, reliability class, and the complete package-to-connector link budget.

When Could CoPoS Enter Mass Production

The current industry forecast points to pilot production in 2027 and mass production in the second half of 2028. Hardware teams should verify the exact package, line, materials, test coverage, and capacity instead of treating a roadmap date as a supply commitment.

The Practical Answer for Hardware Teams

CoPoS is a credible manufacturing path for the largest AI packages, but it will complement CoWoS before it can replace it. The teams most likely to benefit will validate panel yield and reliability with production data while co-designing the package, BGA, PCB stackup, power delivery, cooling hardware, assembly process, and test plan.