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112G PAM4 PCB Design and Manufacturing Guide for AI Servers
KEY TAKEAWAYS
A reliable 112G PAM4 PCB starts with a channel loss budget at the Nyquist frequency, then turns that budget into a low-loss material set, symmetric stackup, controlled transitions, and measurable production requirements. The design is complete only when the fabricator can build the proposed geometry and verify the agreed coupons.
Key Takeaways
Budget the whole channel. Package, traces, vias, pads, connectors, and cables all consume 112G PAM4 margin.
Specify the material system. Lock laminate grade, glass style, resin content, copper profile, and test method.
Co-design the stackup. Use the factory's pressed thickness and finished copper in the field solver.
Define measurable acceptance. Agree on coupons, back drilling, microsections, electrical test, and loss reporting before release.
Introduction
A 112G PAM4 link can fail even when every differential pair looks clean. A short via stub, unmodeled pad, or rough copper foil can consume more margin than several inches of well-designed routing.
This guide turns those risks into practical material, stackup, routing, fabrication, and supplier decisions for AI server hardware.
What Is a 112G PCB
A 112G PCB is a high-speed PCB built for roughly 100 to 112 Gb/s per serial lane using PAM4. Because PAM4 carries two bits per symbol, a 106.25 Gb/s lane runs at about 53.125 GBd, with a 26.6 GHz Nyquist frequency often rounded to 28 GHz for design work.
PAM4 divides the voltage range into three eyes, so it has less vertical margin than NRZ. The board must control insertion loss, return loss, crosstalk, and mode conversion together; nominal impedance alone does not prove 112G PAM4 compliance.
Why AI Servers Are Moving to 112G PAM4
AI servers are moving to 112G PAM4 because GPU clusters need more switch bandwidth without doubling lane count, connector pins, and board area. One 112G-class lane can replace two 56G-class lanes for the same throughput, enabling dense 400G and 800G fabrics.
The tradeoff is a tighter channel budget across long routes, large BGA breakouts, and connectors. Designers must model every discontinuity and verify the complete topology, not rely on length matching alone.
112G PAM4 High Speed PCB Material Selection
Choose material for a 112G PAM4 high-speed PCB by modeled insertion loss, not Tg or one catalog Df value. Compare data from the same test method and frequency, then include copper roughness and finished geometry in the model.
The following screening table shows what the design and procurement teams should lock before fabrication.
| Selection item | Preferred direction | Practical check |
|---|---|---|
| Laminate loss | Very low or ultra-low loss | Use the exact grade and its Dk/Df data at a relevant frequency; do not mix values from different test methods. |
| Copper profile | VLP or HVLP where qualified | Model roughness on critical layers and confirm the foil is available on the selected laminate construction. |
| Glass weave | Spread glass or rotation strategy | Evaluate fiber-weave skew on long pairs and keep both legs over comparable glass and resin regions. |
| Supply control | Approved, traceable material set | Freeze grade, glass style, resin content, foil type, and acceptable substitutions on the drawing. |
Conventional FR-4 may work for a very short 112G PAM4 path, but only after full-channel modeling. Longer reaches usually need a qualified low-loss system such as Megtron 6 or 7 or I-Tera MT40.
112G PAM4 Stackup Structure
A practical 112G PAM4 stackup keeps critical lanes on shallow, tightly referenced layers and mirrors the build around the centerline. An 18- to 24-layer concept may place ground beside shallow stripline layers, keep power distribution near the core, and repeat the structure on the opposite half.
Reference continuity. Place solid ground beside every 112G PAM4 layer; never cross splits or voids.
Short transitions. Use shallow layers where possible to reduce via count, barrel length, reflection, and coupling.
Manufacturable geometry. Solve dielectric thickness, finished copper, trace width, and pair spacing together.
Symmetric construction. Balance copper and dielectric thickness to control bow and twist on large server boards.
Final geometry must use the fabricator's pressed thickness, etch compensation, copper profile, and solder-mask assumptions in a field solver. Never copy a reference stackup unchanged.
Signal Integrity Rules for 112G PAM4 Design
Signal integrity for 112G PAM4 depends on controlling loss, reflections, crosstalk, and skew as one channel rather than optimizing each rule in isolation.
Budget loss at 28 GHz. Allocate insertion loss across package, traces, vias, connectors, and cables. Use the SerDes limit; 30 dB ball-to-ball applies to some long-reach devices, not every link.
Use the specified impedance. Interfaces may call for 85, 90, or 100 ohms differential. Coordinate the package, connector, and board target.
Optimize via transitions. Model drill, pad, antipad, pitch, and ground vias. Back-drill unused barrels; some platforms recommend a residual stub below 10 mil, but simulation and process tolerance set the approved value.
Control intrapair skew. Keep both legs on one layer through symmetric structures and mitigate glass-weave skew with spread glass, routing angle, or placement.
Separate aggressors by risk. Protect attenuated RX lanes from TX coupling with spacing, staggered breakout layers, short parallel barrels, and ground stitching.
Model launch structures. BGA vias, AC-coupling pads, and connectors need S-parameter or 3D analysis; length matching cannot fix resonance.
Run a system-level simulation with transmitter and receiver models, then correlate it with coupon or board measurements. That closes the high-speed PCB design loop.
112G PAM4 Manufacturing Process and Advanced Fabrication
Manufacturing a 112G PAM4 PCB requires the factory to preserve the simulated geometry through material control, imaging, lamination, drilling, plating, and inspection.
1. Engineering review. Freeze stackup, material, foil, impedance, via and back-drill structures, coupons, finish, and acceptance data before CAM release.
2. Inner-layer control. Verify material lots, apply artwork compensation, inspect with AOI, and record post-etch line width.
3. Lamination and registration. Use the qualified press cycle and measure dielectric thickness and alignment.
4. Drilling and back drilling. Remove unused barrels to the specified layer and confirm plating and residual stubs by microsection.
5. Final verification. Complete AOI, open-short testing, dimensions, and TDR coupons. If loss limits apply, agree on the VNA coupon, method, frequency span, and report before production.
Keep first-article records as the baseline for later lots. A material or etch change can alter 112G PAM4 performance even when continuity still passes.
Why PCBgogo Is a Strong 112G PAM4 Manufacturing Partner
A useful 112G PAM4 supplier must connect the customer's loss model to a construction that can be controlled and inspected in production. PCBgogo supports that handoff in four concrete ways.
1. Low-loss materials and high layer counts. PCBgogo lists Megtron 6 and 7, I-Tera MT40, FR408HR, custom stackups, and rigid builds up to 40 layers for server-class designs.
2. Controlled transitions and impedance. Processes include back drilling, blind and buried vias, via-in-pad, resin-filled vias, and sequential lamination. The published back-drill depth tolerance is plus or minus 0.075 mm; tighter prototype impedance is available upon review.
3. Inspection tied to high-speed PCB risk. PCBgogo lists LDI, AOI, automated electrical testing, TDR coupons, and microsection analysis to check geometry, connectivity, impedance, plating, and stub structure.
4. A path from prototype to repeat orders. Published prototype and volume limits help avoid qualifying a one-off build. Send the stackup, impedance matrix, loss limits, material restrictions, and report requirements with the RFQ for 112G PAM4 review.
Summary
A reliable 112G PAM4 high-speed PCB requires a closed loop from channel budget and stackup simulation to measurable fabrication limits. Involve PCBgogo before layout freeze so material, back drilling, coupons, and inspection records are agreed before the first panel.
Frequently Asked Questions
Is 112G PAM4 the same as 112 GBd?
No. PAM4 carries two bits per symbol, so a 106.25 Gb/s lane runs at about 53.125 GBd. 112G PAM4 is a data-rate class, not a 112 GBd symbol rate.
Can standard FR4 be used for a 112G PAM4 PCB?
Only when the modeled channel meets device limits. Very short routes may pass with qualified lower-loss FR-4, but longer high-speed PCB channels usually need very-low-loss laminate and smoother copper.
What differential impedance should a 112G PAM4 channel use?
Use the SerDes, connector, and interface requirements, commonly 85 to 100 ohms differential. A generic 100-ohm rule must not override a 90-ohm interface target.
Does TDR testing prove that a 112G PAM4 channel will pass?
No. TDR verifies impedance versus distance, not insertion loss, return loss, crosstalk, or link performance. Add the interface compliance method and VNA or system testing when required.
What files should be included with a 112G PAM4 PCB quote?
Provide Gerber or ODB++, drill and back-drill files, stackup, finished copper, material and foil requirements, impedance matrix, net list, coupons, IPC class, and reports. Include 112G PAM4 loss limits and the measurement method when the factory must use to verify loss.
